Referring to FIG. 1, the basic voltage-switching (or voltage-mode) CMOS DAC of the prior art includes a thin-film R-2R ladder network 20 and for each leg of the ladder network, a single-pole, double-throw switch. The pole of the switch is connected to the ladder leg; one throw is connected to a reference voltage V.sub.ref and the other throw is connected to analog ground. In practice, the single-pole, double-throw switch is implemented as a pair of MOS switches, generally as indicated at 22. The switches in each pair are complementarily-driven; such as switch pair 24 and 24 , they consist of a V.sub.ref (reference voltage) switch (e.g., 24.sub.1) and an Agnd (analog ground) switch (e.g.. 24.sub.0) Only one of the switches in each pair is on at any moment, due to complementary operation. The state of each switch pair is determined by a corresponding one of the digital code bits supplied to the converter's digital input. The ladder network termination resistor 26 is connected to Agnd via a permanently "ON" Agnd switch 28.sub.0.
In practice, ideal switches cannot be fabricated; each MOS switch has a finite "ON" resistance, rather than a zero resistance. While this finite resistance is small, it is not inconsequential and it can affect DAC accuracy. To minimize error and make high accuracy DACs using these non-ideal switches, the following rules generally are employed:
First, the switch "ON" resistance, R.sub.ON, is binarily scaled from bit to bit. PA1 Second, the R.sub.ON s of the V.sub.ref switch and Agnd switch in each pair are matched. PA1 V.sub.TV =threshold voltage of the V.sub.ref switch PA1 V.sub.DSV =drain-source voltage of the V.sub.ref switch PA1 V.sub.TA =threshold voltage of the Agnd switch PA1 V.sub.DSA =drain source voltage of the Agnd switch
A number of circuit techniques have been developed to produce matched switches. Referring to FIG. 2, a first type of prior art switch pair 30 is formed of a V.sub.ref switch transistor 30.sub.1 and an Agnd switch transistor 30.sub.0, both of which are n-channel devices. This is the simplest switching scheme and is primarily employed when a conventional, current switching (or current mode) DAC is used in voltage-switching mode. Such a circuit presents an inherent mismatch of R.sub.ON values, caused primarily by a mismatch in gate-source voltages (i.e V.sub.gs). Moreover, the R.sub.ON mismatch worsens as V.sub.ref increases.
In another prior art embodiment shown in FIG. 3, a first order cancellation of this mismatch is achieved by appropriate device geometry scaling.
This design has a higher upper limit for the reference voltage, but also suffers some disadvantages. For example, increased die area is required, as each V.sub.ref switch requires its own p-well. Further, the reference voltage is restricted to values close to the particular value for which the ratios of width to length achieve first order compensation of V.sub.gs mismatch.
In yet another case, showed in FIG. 4, the "ON" gate voltage of the Agnd switch 34.sub.0 is adjusted in accordance with the value of V.sub.ref, thus eliminating the V.sub.gs mismatch and achieving good "ON" resistance matching that of the V.sub.ref switch. The FIG. 4 approach is more fully explained in Tuthill et al., U.S. Pat. No. 4,558,242 issued Dec. 10, 1985, to as the present invention. The Tuthill, et al. patent contains a more detailed discussion of the other prior art switches of FIGS. 2 and 3 also, as well as their characteristics and compensation, and is hereby incorporated by reference for those discussions.
The embodiment of FIG. 4 adjusts the "ON" gate voltage of the Agnd switch according to the value of V.sub.ref , to provide V.sub.gs equality (and thus, R.sub.ON matching) over a wider reference range. From U.S. Pat. No. 4,558,442, the following salient observations may be made of the switch pair of FIG. 4. First, the V.sub.ref and the Agnd switches are of the same size. Second, the switch devices occupy separate p-wells. Third, the "ON" gate voltage of the Agnd switch is V.sub.dd -V.sub.ref, whereas that of the V.sub.ref switch is V.sub.dd. Good R.sub.ON matching is achieved by having V.sub.dd -V.sub.ref much larger than V.sub.TV +V.sub.DSV or V.sub.TA -V.sub.DSA, where
A practical implementat1on of the scheme of FIG. 4 involves the design of an Agnd switch "ON" gate voltage generator circuit 40 as illustrated in FIG. 5. This "V.sub.dd -V.sub.ref " generator circuit drives the positive power rail for all the Agnd switch drivers. In general, an op0amp circuit 42, shown in FIG. 6, can be used to implement this function, but FIG. 7 shows a more specific integrated circuit implementation 44. FIG. 8 shows how the Agnd switch drivers 46 are driven from generator circuit 44 (or 42).
All of the prior art schemes illustrated in FIGS. 2-4, it should be noted, use n-channel MOSFETs. However, the use of n-channel MOSFET's requires that the gate of the V.sub.ref switch be driven by a voltage sufficiently greater than V.sub.ref as to achieve the desire R.sub.ON. This means that V.sub.ref has to be several volts lower than the most positive supply voltage, which, in turn, restricts the potential range of the output signal swing for such a converter.
Accordingly, it is an object of the invention to provide an improved switching circuit for CMOS voltage-switching DACs.
A further object of the invention is to provide in a CMOS voltage-switching DAC, a switching circuit which can maintain a substantial signal swing even under low supply voltage conditions.
Yet another object of the invention is to provide a switching circuit which requires only small die area.
Still another object of the invention is to provide a switching circuit which provides dynamic matching of R.sub.ON values.
A still further object of the invention is to provide a switching circuit which does not require the generation of complementary switching signals and thereby provides an opportunity to better match the timing of device switching.